In recent years, the operation speed of a semiconductor device increases remarkably. Especially, a semiconductor device which can transmit a signal in a high transmission rate of 5 Gbps or more in a low cost is demanded. Accordingly, a semiconductor package and interposer package with high performance in a low cost are required in order to protect the semiconductor chip and to connect with a system board.
The interposer package which is provided with a stripline or a micro stripline in many printed circuit boards has advantageous electric properties in transmission of a signal in a high transmission rate. However, such an interposer package is expensive as compared with a lead frame-type package such as QFP (Quad Flat Package) which is conventionally used.
Therefore, a trial has been made to transmit a signal in a high transmission rate by using a lead frame-type package of a low cost, as described in Non-Patent Literature 1, “Design of Low Cost QFP Packages for Multi-Gigabit Memory Interface” (Proceedings of 59th Electronic Components and Technology Conference, 1662 (2009)) by Joong-Ho Kim, Ralf Schmitt, Dan Oh, Wendemagegnehu T. Beyene, Ming Li, Arun Vaidyanath, Yi Lu, June Feng, Chuck Yuan, Dave Secker, and Don Mullen.
However, in the lead frame-type package which does not have a plane conductor as a reference (a return path), basically, impedance of a signal lead pin is high. Also, in such a signal lead pin, coupling with another lead pin is strong. For this reason, it is difficult to transmit the signal in the high transmission rate of 5 Gbps or more in high quality.
In order to solve this problem, in Patent Literature 1 (U.S. Pat. No. 6,576,983), a special structure of the semiconductor package having a signal reference plane is proposed. FIG. 1 is a section view showing the structure of the semiconductor package disclosed in Patent Literature 1.
However, the structure disclosed in Patent Literature 1 is expensive. Accordingly, it is desirable to achieve signal transmission in the high transmission rate by using as many existing manufacturing processes as possible.
Generally, the lead frame type package has basic problems. The first problem is in that the lead frame-type package does not have a conductor as the reference for the signal transmitted in the high transmission rate. The second problem is in that the coupling between two neighbor signal pins is very strong. Because of these two problems, the impedance of a signal pin is high so that a large signal reflection occurs and also a large inter-signal interference (crosstalk) occurs. As a result, a signal waveform degrades to cause a data detection error.
The property peculiar to the lead frame-type package causes a problem when differential signal interconnection generally used in a device having a transmission rate of Gbps or more is configured. This is because the coupling between two lead pins for a differential signal is too strong.
To perform transmission in a high transmission rate, it is required to appropriately control impedances in two modes in the differential signal, i.e. a differential mode and a common mode. Here, the impedance in the differential mode is smaller than twice of the impedance of a single signal pin due to the coupling between signal pins. For the same reason, the impedance in the common mode is larger than a half of the impedance of the single signal pin. Also, as the coupling between the signal pins becomes stronger, the deviation from twice or the half becomes larger. It should be noted that an ideal value of the differential mode impedance is 100Ω and an ideal value of the common mode impedance is 25Ω.
It could be easily understood that the lead frame-type package in which the coupling between the signal pins is strong has a very high common mode impedance, because even the impedance of the single pin is high.
Generally, when the common mode impedance in a signal route to an input/output circuit on a semiconductor device is very high, large common mode noise generates on the signal route. This causes the generation of EMI (ElectroMagnetic Interference). This mechanism could be understood as follows.
Ideally, a differential signal output circuit should output only an ideal differential signal. However, in an actual circuit, some amount of common mode signal is generated. This common mode signal is divided in voltage based on an impedance ratio of the output impedance of the output circuit and the impedance of the signal route. Generally, in a GHz band, the impedance of the output circuit is low because of its parasitic capacitance. Therefore, when the impedance of the signal route is high, the common mode signal is taken out to the signal route in efficiency near to 100%. That is, an unwanted common mode signal (to be sometimes referred to as a common mode noise because it is unnecessary) causing the EMI is efficiently appeared on the signal route.
Moreover, according to the definition of the impedance, the fact that the common mode impedance in the signal route is high means that the signal route efficiently converts a noise current introduced from the vicinity into the common mode noise. The noise current is mainly induced due to a magnetic field generated from the signal route. Though it has been described above that electromagnetic radiation is easily generated when the common mode impedance is high, it could be understood that the sensitivity to the electromagnetic radiation, too, is high. That is, though it is not only easy to generate the electromagnetic radiation, but also weak to the electromagnetic radiation. Therefore, it is easy to understand that there occurs positive feedback. It is important to control the common mode impedance in addition to the crosstalk.
When a signal transmission is performed in the transmission rate of 5 Gbps or more, the degradation of a signal waveform due to a parasitic capacitance of the I/O circuit regardless of a kind of a package or an interposer will be described in Non-Patent Literature 2, i.e. “Novel T-Coil Structure and Implementation in a6.4-Gb/s CMOS Receiver to Meet Return Loss Specification” (Proceeding of 57th Electronic Components and Technology Conference, 147 (2007)) by Edward Pillai, and Jonas Weiss and Non-Patent Literature 3, i.e. “Package Substrate Built-In Three-Dimensional Distributed Matching Circuit for high-Speed SerDes Applications” (Proceeding of 58th Electronic Components and Technology Conference, 676 (2008)) by Ryuichi Oikawa.
Non-Patent Literature 2 describes a measure on an LSI circuit. Non-Patent Literature 3 describes a measure on a package/interposer. These measures have merits and demerits. However, the measures on the package and interposer are desirable for the purpose that the measures are achieved by using conventional manufacturing technique as much as possible in a low cost.
As discussed above, it is necessary to solve the above problems of the signal degradation due to the absence of the signal reference, the large signal crosstalk, the high common mode impedance, and the parasitic capacitance of the I/O circuit, in order to achieve the high-speed signal transmission of 5 Gbps or more on the lead frame-type package or interposer in low cost.
FIG. 2A is a plan view showing the outward appearance of a semiconductor device disclosed in Patent Literature 2 (U.S. Pat. No. 7,009,282). FIG. 2B is a plan view showing the structure of a lead frame-type package disclosed in Patent Literature 2.
In the conventional techniques shown in FIGS. 2A and 2B, a “pitch extension pin” is provided between two pins. That is, the reduction of crosstalk between the pins is attempted by extending a pin interval partially. There are drawbacks that the number of usable pins is decreased and that footprint is out of a usual design process in mounting on a printed circuit board in this technique. However, because a distance between the pins can be extended several times by providing the pitch extension pin, a crosstalk is considerably reduced.
It is possible to reduce the common mode impedance to a differential signal by assigning the differential signal to two pins provided to have a long interval, although it is not specially described in Patent Literature 2. However, because the impedance per one pin remains high, a large effect is not obtained.
FIG. 3A is a perspective view showing a structure of a two-dimensional array-type connector disclosed in Patent Literature 3 (U.S. Pat. No. 7,467,955). FIG. 3B is a plan view showing interconnection of the two-dimensional array-type connector disclosed in Patent Literature 3.
In the conventional technique shown in FIGS. 3A and 3B, the ground voltage is properly allocated to a part of lead pins at the two-dimensional array-type connector so that the part of lead pins acts as a signal return path or an inter-signal shield. Further, FIG. 3B includes a contour plot of voltage in the neighborhood of an active column-based differential signal pair S− S—in contact arrangement of signal contacts S and ground contacts G. As shown, contour lines 42 are closest to zero volts, contour lines 44 are closest to -1 volt, and contour lines 46 are closest to +1 volt. Even if only one line of the two-dimensional array structures shown in FIGS. 3A and 3B is taken out, the same effect as in the two-dimensional array structure is not obtained, but it would be applicable to a lead frame-type package of a semiconductor device. Also, a method of adjusting a signal pin interval and a signal pin width to adjust impedances and a method of arranging a pair of pins for a differential signal and a pin for the ground voltage alternately to reduce a crosstalk are disclosed in Patent Literature 3. However, a method of controlling common mode impedance is not described in Patent Literature 3 especially.